F-RAM Technology Brief

Overview

Established semiconductor memory technologies are divided into two categories: 1. RAMs are Random Access Memories, which simply means that the access time for reads and writes are symmetric. 2. Nonvolatile memories have traditionally been ROM (Read Only Memory) until the advent of floating gate technology, which produced electrically erasable memories such as Flash and EEPROM. These products allow for in-system programming but read and write access times are dissimilar. In fact, the write access times can be several orders of magnitude greater than the read access times. Ferroelectric Random Access Memory or F-RAM has attributes that make it the ideal nonvolatile memory. It is a true nonvolatile RAM. The write advantages and non-volatility make it quite suitable for storing data in the absence of power.

Ferroelectric Property

La proprieta' ferroelettrica e' un fenomeno osservato in una classe di materiali noti come Perovskite. In Figura 1 e' mostrato un cristallo di Perovskite. L'atomo posto al centro ha due livelli di energia bassa stabili e uguali. Questi stati determinano la posizione dell'atomo. Se un campo elettrico e' applicato nel piano gli atomi si muoveranno nella direzione del campo. Applicando un campo elettrico attraverso il cristallosi 

The ferroelectric property is a phenomena observed in a class of materials known as Perovskites. Figure 1 shows a Perovskite crystal. The atom in the center has two equal and stable low energy states. These states determine the position of the atom. If a field is applied in the proper plane, the atom will move in the direction of the field. Applying an electric field across the crystal causes the low energy state or position to be in the direction of the field and, conversely, the high energy state in the opposite position. The applied field will, therefore, cause the atom to move from the high energy state to the low energy state. This transition produces energy in the form of charge generally referred to as switch charge (Qs). Therefore, applying an alternating electric field across the crystal will cause the atom to move from the top of the crystal to the bottom and back again. Each transition will produce charge, Qs.

Figure 1. Ferroelectric (Perovskite) Crystal

A common misconception is that ferroelectric crystals are ferromagnetic or have similar properties. The term ferroelectric refers to similarity of the graph of charge plotted as a function of voltage (Figure 2) to the hysteresis loop (BH curve) of ferromagnetic materials. Ferroelectric materials switch in an electric field and are not affected by magnetic fields.

Figure 2. Ferroelectric Hysteresis Loop

The ferroelectric material has two states, the atom at the top, which is referred to as up polarization, and the atom at the bottom, which is referred to as down polarization (Figure 3). Therefore, with a viable sensing scheme a binary memory can be produced.

Figure 3. Crystal Polarization

F-RAM Operation 

Il capacitore Ferroelettrico

L'elemento base di memoria e' il condensatore ferroelettrico. Il capacitore puo essere polarizzato in due stati possibiliThe capacitor can be polarized up or down by applying a field (Figure 4).

Figure 4. Ferroelectric Capacitor Polarization

Il simbolo del capacitore ferroelettrico indica che la capacità e' variabile e che non e' un tradizionale capacitore lineare. Se il capacitore non commuta lo stato quando un campo elettrico e' applicato ( non si ha cambiamento nella polarizzazione) esso si comporta come un capacitore lineare. Se questo invece commuta , u

The ferroelectric capacitor symbol indicates that the capacitance is variable and is not a traditional linear capacitor. If a ferroelectric capacitor is not switched when an electric field is applied (no change in polarization), it behaves like a linear capacitor. If it is switched, there is an additional charge induced, hence the capacitance must increase. The ferroelectric capacitor is combined with an access transistor, a bit line, and a plate line to form the memory cell (Figure 5).

Operazione di Lettura 

The static state of the cell is Bit Line low, Plate Line low, Word Line low (Figure 6A). The access begins by applying voltage to the Word Line and the Plate Line (6B). This applies a field across the ferroelectric capacitor and the ferroelectric capacitor switches (6C). The induced charge (Qs) is shared with the parasitic Bit Line capacitance (Cbit) and the switched ferroelectric capacitor (Cs). The voltage on the bit line, therefore, is proportional to the ratio of the capacitances Cs/Cbit (Cs includes a small contribution from transistor and interconnect parasitics).

Figure 6. Memory Cell Access Sequence

Figure 6 shows the switched case. Had the polarization been up in this sequence, the capacitor would not switch and there would be no additional charge induced. The charge induced in the switched capacitor is at least two times greater than the charge available in the unswitched capacitor (Qu). Qs e 2Qu. Therefore, the switched capacitance (Cs) is at least twice the unswitched capacitance (Cu). Cs e 2Cu It follows that the Bit Line voltage for the switched case is at least two times greater then the Bit Line voltage for the unswitched case. The sensing scheme is very similar to the techniques used in DRAMs. The Bit Line voltage is simply compared to a reference that is above the unswitched value and below the switched value. The sense amp drives the Bit Lines to the rails and the output of the sense amp is either high or low (1 or 0). The access is completed in less than 100ns. At the end of the access the Bit Lines are set high for the switched case and set low for the unswitched case. The cycle is completed by bringing the Plate Line low, which restores the state of the switched terms and then the Bit Line is precharged to 0V. The restore/precharge period is also very fast, less than 100ns. The minimum achievable access/cycle times are primarily driven by the capacitance of the memory cell. The time it takes to switch the ferroelectric capacitor is nearly instantaneous and, therefore, switching mechanisms does not contribute to the overall cycle time. The sensing scheme is similar to DRAMs because both F-RAM and DRAM sense charge. The charge in a DRAM is stored in a linear capacitor that leaks and requires refresh. The charge in an F-RAM is stored as state in the crystal and is, therefore, nonvolatile and requires no refresh. Like DRAMs, F-RAMs have a cycle time, so the minimum time between back-toback random addresses is equal to the cycle time, not the access time. Today, typical cycle times are less than 200ns and in the near future should be less the 100ns.

Write Operation

A write operation is very similar to a read operation. The circuit simply applies a field in the desired direction across the ferroelectric capacitor.

Una operazione di scrittura è molto simile ad una operazione di lettura. Il circuito semplicemente applica un campo nella direzione desiderata in tutto il condensatore ferroelectric.

F-RAM Benefits

Traditional writable nonvolatile memories derived from floating gate technology use charge pumps to develop high voltage on-chip (10V or more) to force carriers through the gate oxide. Therefore, there are long write delays, high write power, and the write operation is actually destructive to the memory cell. Floating gate devices are incapable of supporting writes that exceed 106 accesses. To put this in perspective, a data recorder using EEPROM that was recording data at 1 sample/s would wear out in less than 12 days. In comparison, the 3V F-RAM products offer virtually unlimited endurance (10e15 accesses). The F-RAM is far superior to floating gate devices in both write speed and power. For a typical serial EEPROM with a clock rate of 20MHz, it will take 5ms to write 32 bytes (page buffer). For an equivalent F-RAM, it will take 2ms to write 4K bytes. In addition, it requires 10.5mJ to write 4K bytes for the EEPROM versus 27µJ to write 4K bytes to an F-RAM.In summary: * Read Access Time * Write Access Time <100ns * Read Energy * Write Energy * * High Write Endurance>

Di scrittura tradizionale non volatile memorie derivati da galleggianti cancello carica di uso della tecnologia per sviluppare le pompe ad alta tensione su chip (10V o più) per forzare i vettori attraverso la porta di ossido. Pertanto, non vi sono lunghi ritardi scrivere, scrivere ad alta potenza, e la operazione di scrittura è distruttiva per la cella di memoria. Floating gate dispositivi sono in grado di sostenere scrive che superi il 106 accessi. A mettere in questa prospettiva, un registratore dei dati utilizzando EEPROM che è stata la registrazione dei dati a 1 campione / s si usura in meno di 12 giorni. In confronto, i 3V F-RAM offrire prodotti virtualmente illimitato di resistenza (10e15 accessi). F-RAM è di gran lunga superiore a galleggiante porta in entrambi i dispositivi di velocità di scrittura e di potere. Per una tipica EEPROM seriale con una frequenza di clock di 20MHz, ci vorranno 5ms di scrivere 32 byte (buffer di pagina). Per un equivalente F-RAM, ci vorranno 2ms per scrivere 4K byte. Inoltre, si richiede 10.5mJ per scrivere 4K byte per la EEPROM versus 27 μ J scrivere 4K bytes ad un F-RAM.In sommario: Leggi * Tempo di accesso * Scrivi Tempo di accesso <100ns * Energia * Leggi Scrivi Energia * * Alta Scrivi Endurance

Applicazioni delle memorie Feram

1. Power failure

Any nonvolatile memory can retain a configuration. However, if the configuration changes and power failure is a possibility, the higher write endurance of F-RAM allows changes to be recorded without restriction. Any time the system state changes, it writes the new state. This avoids writing to memory on power down when the available time is short and power is disappearing.

Qualsiasi memoria non volatile e' in grado di mantenere una configurazione. Tuttavia, se le modifiche di configurazione e di potenza fallimento è una possibilità, la più elevata resistenza scrivere di F-RAM permette modifiche devono essere registrate senza restrizioni. Qualsiasi momento lo stato del sistema cambia, scrive il nuovo Stato. In questo modo si evita la scrittura di memoria a spegnere quando il tempo a disposizione è poco e il potere è scomparsa.

2. RF/ID

F-RAM Technology Brief Traditional writable nonvolatile memories derived from floating gate technology use charge pumps to develop high voltage on-chip (10V or more) to force carriers through the gate oxide. Therefore, there are long write delays, high write power, and the write operation is actually destructive to the memory cell. Floating gate devices are incapable of supporting writes that exceed 106 accesses. To put this in perspective, a data recorder using EEPROM that was recording data at 1 sample/s would wear out in less than 12 days. In comparison, the 3V F-RAM products offer virtually unlimited endurance (1015 The F-RAM is far superior to floating gate devices in both write speed and power. For a typical serial EEPROM with a clock rate of 20MHz, it will take 5ms to write 32 bytes (page buffer). For an equivalent F-RAM, it will take 2ms to write 4K bytes. In addition, it requires 10.5mJ to write 4K bytes for the EEPROM versus 27µJ to write 4K bytes " Read Access Time = Write Access Time <100ns " Read Energy = Write Energy " High Write Endurance Any nonvolatile memory can retain a configuration. However, if the configuration changes and power failure is a possibility, the higher write endurance of F-RAM allows changes to be recorded without restriction. Any time the system state changes, it writes the new state. This avoids writing to memory on power down when the available time is short and In the area of contactless memory, F-RAM provides an ideal solution. Since RF/ID memory is powered by an RF field, and the available energy in the field declines exponentially with distance, low energy access is critical. The tag must be close enough to the field to induce the minimum amount of energy to write and it must extract the energy while in the field. Applications that require writes (e.g. debit cards, tags used in manufacturing processes) benefit from improved write distance, lower sensitivity to motion (time in the field), and lower RF power required for the transmitter /receiver.

3. High noise environments

Le memorie Feram mostrano una buona immunità al rumore durante la fase di scrittura. Scrivere una memoria EEPROM in un ambiente rumoroso può essere difficile. Quando molto rumore elettrico e fluttuazioni della alimentazione sono presenti, il lungo tempo di scrittura di una EEPROM crea un finestra temporale di vulnerabilità (misurata in millisecondi) durante la quale la scrittura può essere corrotta. La probabilità di errore e' proporzionale alla durata di questa finestra temporale. La finestra temporale in cui avviene la scrittura di una memoria Feram e' dell'ordine dei 200ns e quindi la probabilità che la scrittura venga corrotta in un ambiente rumoroso e' molto bassa.

4. Diagnostica/Maintenance

In sistemi sofisticati, la conoscenza della storia del funzionamento e dello stato del sistema durante un fallimento sono di notevole importanza perché permette di risolvere i problemi. Per la loro elevata capacita di mantenere il dato scritto, le memorie Feram sono ideali per realizzare un log di sistema.