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MST_K12 - DC MOTOR SPEED REGULATOR |
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Architecture description In figure 2 the block diagram of the MST_K12 is reported. The potenziometer generates a control voltage VC that is sampled and converted by the ADC peripheral of the microcntroller. The ADC convertion result defines the PWM duty cycle . The PWM signal is carriered out to the power MOS gate by a level traslator to drive the POWER MOS at the supply voltage. The POWER MOS is in open drain configuration so he load must be connected between the supply voltage and its drain. The control method of the speed is in OPEN LOOP so the speed is not compared with a reference and the real motor speeddependsby the load condition fo he motor. The supply of the circuit is derived from the power supply applied at the terminals V+, V- and it is regulated at the 5V by a low drop voltage regulator.
Fig. 2: block diagram of the MST_K12 DC motor speed regulator |
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